#ifndef __HAL_SPEC_DEFINE_H
#define __HAL_SPEC_DEFINE_H

#define TIMING_PLL_PXIN         24
#define TIMING_PLL_FOUT_DIV     2           /* FOUT1-2; FOUT2-4; FOUT3-6; FOUT4-8*/
#define TIMING_PLL_POSTDIV1_MAX 7
#define TIMING_PLL_FOUTVCO_MIN  800000000ul
#define TIMING_PLL_FOUTVCO_MAX  3200000000ul
#define TIMING_PLL_FBDIV_MIN    20
#define TIMING_PLL_FBDIV_MAX    360         /* (0~2^24) */
#define TIMING_PLL_FRAC_MAX     1048576     /* (0~2^24) */


typedef enum tagDISP_INTERRUPT_E
{
    DISP_INTERRUPT_NONE = 0,
    DISP_INTERRUPT_D0_0_PERCENT  = 0x10,
    DISP_INTERRUPT_D0_90_PERCENT = 0x20,
    DISP_INTERRUPT_D0_100_PERCENT = 0x40,
    DISP_INTERRUPT_D0_UFINT      = 0x80,

    DISP_INTERRUPT_D1_0_PERCENT  = 0x1,
    DISP_INTERRUPT_D1_90_PERCENT = 0x2,
    DISP_INTERRUPT_D1_100_PERCENT = 0x4,
    DISP_INTERRUPT_D1_UFINT      = 0x8,

    DISP_INTERRUPT_WBCDHD_PARTFNI  = 0x20000000,

    DISP_INTERRUPT_GP1_RES       = 0x100,
    DISP_INTERRUPT_MC1_UFINT     = 0x200,
    DISP_INTERRUPT_WBC_VP    = 0x800,

    DISP_INTERRUPT_ALL           = 0xFFFFFFFF,
} DISP_INTERRUPT_E;



#define VDP_CLK_MODE_333MHZ     0
#define VDP_CLK_MODE_300MHZ     1

#define CLOCK_DIV_1  3
#define CLOCK_DIV_2  0
#define CLOCK_DIV_4  1
#define CLK_HDMI_VO_1_1  0
#define CLK_HDMI_VO_1_2  1

typedef enum hiVDP_CLOCK_WORK_CLK_E
{
    VDP_CLOCK_WORK_CLK_ALL = 0,
    VDP_CLOCK_WORK_CLK_HALF,
    VDP_CLOCK_WORK_CLK_QUARTER,
    VDP_CLOCK_WORK_CLK_BUTT
} HI_VDP_CLOCK_WORK_CLK_E;

#endif
